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PIC18F2450/4450

2006 Microchip Technology Inc.

Advance Information

DS39760A-page 137

14.4

Buffer Descriptors and the Buffer

Descriptor Table

The registers in Bank 4 are used specifically for end-

point buffer control in a structure known as the Buffer

Descriptor Table (BDT). This provides a flexible method

for users to construct and control endpoint buffers of

various lengths and configuration.

The BDT is composed of Buffer Descriptors (BD) which

are used to define and control the actual buffers in the

USB RAM space. Each BD, in turn, consists of four

registers, where n represents one of the 64 possible

BDs (range of 0 to 63):

BDnSTAT: BD Status register

BDnCNT: BD Byte Count register

BDnADRL: BD Address Low register

BDnADRH: BD Address High register

BDs always occur as a four-byte block in the sequence,

BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address

of BDnSTAT is always an offset of (4n – 1) (in

hexadecimal) from 400h, with n being the buffer

descriptor number.

Depending

the

buffering

configuration

used

(Section 14.4.4 “Ping-Pong Buffering”), there are up

to 32, 33 or 64 sets of buffer descriptors. At a minimum,

the BDT must be at least 8 bytes long. This is because

the USB specification mandates that every device must

have Endpoint 0 with both input and output for initial

setup. Depending on the endpoint and buffering

configuration, the BDT can be as long as 256 bytes.

Although they can be thought of as Special Function

Registers, the Buffer Descriptor Status and Address

registers are not hardware mapped, as conventional

microcontroller SFRs in Bank 15 are. If the endpoint cor-

responding to a particular BD is not enabled, its registers

are not used. Instead of appearing as unimplemented

addresses, however, they appear as available RAM.

Only when an endpoint is enabled by setting the

UEPn<1> bit does the memory at those addresses

become functional as BD registers. As with any address

in the data memory space, the BD registers have an

indeterminate value on any device Reset.

A total of 256 bytes of address space in Bank 4 is

available for BDT and USB data RAM. In Ping-Pong

Buffer mode, all the 16 bidirectional endpoints can not

be implemented where BDT itself can be as long as

256 bytes. In the majority of USB applications, few

endpoints are required to be implemented. Hence, a

small portion of the 256 bytes will be used for BDT and

the rest can be used for USB data.

An example of a BD for a 16-byte buffer, starting at

480h, is shown in Figure 14-6. A particular set of BD

registers is only valid if the corresponding endpoint has

been enabled using the UEPn register. All BD registers

are available in USB RAM. The BD for each endpoint

should be set up prior to enabling the endpoint.

14.4.1

BD STATUS AND CONFIGURATION

Buffer descriptors not only define the size of an

endpoint buffer, but also determine its configuration

and control. Most of the configuration is done with the

BD Status register, BDnSTAT. Each BD has its own

unique and correspondingly numbered BDnSTAT

FIGURE 14-6:

EXAMPLE OF A BUFFER

DESCRIPTOR

Unlike other control registers, the bit configuration for

the BDnSTAT register is context sensitive. There are

two distinct configurations, depending on whether the

microcontroller or the USB module is modifying the BD

and buffer at a particular time. Only three bit definitions

are shared between the two.

14.4.1.1

Buffer Ownership

Because the buffers and their BDs are shared between

the CPU and the USB module, a simple semaphore

mechanism is used to distinguish which is allowed to

update the BD and associated buffers in memory.

This is done by using the UOWN bit (BDnSTAT<7>) as

a semaphore to distinguish which is allowed to update

the BD and associated buffers in memory. UOWN is the

only bit that is shared between the two configurations

of BDnSTAT.

When UOWN is clear, the BD entry is “owned” by the

microcontroller core. When the UOWN bit is set, the BD

entry and the buffer memory are “owned” by the USB

peripheral. The core should not modify the BD or its

corresponding data buffer during this time. Note that

the microcontroller core can still read BDnSTAT while

the SIE owns the buffer and vice versa.

The buffer descriptors have a different meaning based

on the source of the register update. Prior to placing

ownership with the USB peripheral, the user can con-

figure the basic operation of the peripheral through the

BDnSTAT bits. During this time, the byte count and

buffer location registers can also be set.

400h

USB Data

Buffer

BD0STAT

BD0CNT

BD0ADRL

BD0ADRH

401h

402h

403h

480h

48Fh

Descriptor

Note:

Memory regions not to scale.

10h

80h

04h

Starting

Size of Block

(xxh)

Registers

Address

Contents

Address

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